About: ECC Memory for Fault Tolerant RISC-V Processors

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An Entity of Type : schema:ScholarlyArticle, within Data Space : wasabi.inria.fr associated with source document(s)

Attributes	Values
type	Academic Article research paper schema:ScholarlyArticle
isDefinedBy	Covid-on-the-Web dataset
title	ECC Memory for Fault Tolerant RISC-V Processors
Creator	Dörflinger, Alexander Guan, Yejun Michalik, Harald Michalik, Sönke Michalik, Sören Naghmouchi, Jamin
source	PMC
abstract	Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed.
has issue date	2020-06-12(xsd:dateTime)
bibo:doi	10.1007/978-3-030-52794-5_4
has license	no-cc
sha1sum (hex)	1675334e66a53b7b94318089fd3a6da9770e0974
schema:url	https://doi.org/10.1007/978-3-030-52794-5_4
resource representing a document's title	ECC Memory for Fault Tolerant RISC-V Processors
has PubMed Central identifier	PMC7343426
schema:publication	Architecture of Computing Systems - ARCS 2020
resource representing a document's body	covid:1675334e66a53b7b94318089fd3a6da9770e0974#body_text
is schema:about of	named entity 'automotive' named entity 'CHIPS' named entity 'Set' named entity 'RISC-V' named entity 'safety-critical' named entity 'Error Correction' named entity 'fault tolerance' named entity 'ECC' named entity 'concepts' named entity 'Error Correction Code' named entity 'ASICs' named entity 'clock cycle' named entity 'Instruction Set Architecture' named entity 'MHz' named entity 'soft error' named entity 'Xilinx' named entity 'RISC-V' named entity 'RISC-V' named entity 'ECC' named entity 'fault tolerance' named entity 'memory interface' named entity 'RISC-V' named entity 'FPGA' named entity 'error correction' named entity 'ported' named entity 'UC Berkeley' named entity 'fault-tolerant' named entity 'SoC' named entity 'soft errors' named entity 'ECC' named entity 'standard cell libraries' named entity 'non-blocking' named entity 'embedded memory' named entity 'NOEL' named entity 'multiplexers' named entity 'RISC-V' named entity 'ECC' named entity 'non-blocking' named entity 'voltage' named entity 'high performance computing' named entity 'L1D' named entity 'ECC' named entity 'Error Detection' named entity 'SEC' named entity 'FPGA' named entity 'error detection' named entity 'clock cycles' named entity 'write-back' named entity 'built-in self-test' named entity 'memory hierarchy' named entity 'instruction cache' named entity 'SEC-DED' named entity 'error correction' named entity 'on-chip' named entity 'L1I' named entity 'Microsemi' named entity 'algorithm' named entity '64 bit' named entity 'Cache line' named entity 'ECC' named entity 'inputs and outputs' named entity 'Single Event Effects' named entity 'nonblocking' named entity 'error rates' named entity 'fault tolerance' named entity 'ASIC' named entity 'ECC' named entity '2-bit' named entity 'ECC' named entity 'hardware description language' named entity 'free and open' named entity 'parity bit' named entity 'load distribution' named entity 'safety-critical' named entity 'debug' named entity 'ECC' named entity 'ECC' named entity 'Fault tolerance'

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