About: Investigating Transactional Memory for High Performance Embedded Systems

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An Entity of Type : schema:ScholarlyArticle, within Data Space : wasabi.inria.fr associated with source document(s)

Attributes	Values
type	Academic Article research paper schema:ScholarlyArticle
isDefinedBy	Covid-on-the-Web dataset
has title	Investigating Transactional Memory for High Performance Embedded Systems
Creator	Altmeyer, Sebastian Amslinger, Rico Haas, Florian Piatka, Christian Ungerer, Theo Weis, Sebastian
Source	PMC
abstract	We present a Transaction Management Unit (TMU) for Hardware Transactional Memories (HTMs). Our TMU enables three different contention management strategies, which can be applied according to the workload. Additionally, the TMU enables unbounded transactions in terms of size. Our approach tackles two challenges of traditional HTMs: (1) potentially high abort rates, (2) missing support for unbounded transactions. By enhancing a simulator with a transactional memory and our TMU, we demonstrate that our TMU achieves speedups of up to 4.2 and reduces abort rates by a factor of up to 11.6 for some of the STAMP benchmarks.
has issue date	2020-06-12(xsd:dateTime)
bibo:doi	10.1007/978-3-030-52794-5_8
has license	no-cc
sha1sum (hex)	60b2e96419abcb943a58e64cac33961543ce03b7
schema:url	https://doi.org/10.1007/978-3-030-52794-5_8
resource representing a document's title	Investigating Transactional Memory for High Performance Embedded Systems
has PubMed Central identifier	PMC7343417
schema:publication	Architecture of Computing Systems - ARCS 2020
resource representing a document's body	covid:60b2e96419abcb943a58e64cac33961543ce03b7#body_text
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