About: Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions

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An Entity of Type : schema:ScholarlyArticle, within Data Space : wasabi.inria.fr associated with source document(s)

Attributes	Values
type	Academic Article research paper schema:ScholarlyArticle
isDefinedBy	Covid-on-the-Web dataset
has title	Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions
Creator	Strejček, Jan Jonáš, Martin
Source	PMC
abstract	Recent experiments have shown that satisfiability of a quantified bit-vector formula coming from practical applications almost never changes after reducing all bit-widths in the formula to a small number of bits. This paper proposes a novel technique based on this observation. Roughly speaking, a given quantified bit-vector formula is reduced and sent to a solver, an obtained model is then extended to the original bit-widths and verified against the original formula. We also present an experimental evaluation demonstrating that this technique can significantly improve the performance of state-of-the-art smt solvers Boolector, CVC4, and Q3B on quantified bit-vector formulas from the smt-lib repository.
has issue date	2020-06-26(xsd:dateTime)
bibo:doi	10.1007/978-3-030-51825-7_27
has license	no-cc
sha1sum (hex)	80da8bb8d3ed245e2f8121d6d3aa859506e81929
schema:url	https://doi.org/10.1007/978-3-030-51825-7_27
resource representing a document's title	Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions
has PubMed Central identifier	PMC7326550
schema:publication	Theory and Applications of Satisfiability Testing - SAT 2020
resource representing a document's body	covid:80da8bb8d3ed245e2f8121d6d3aa859506e81929#body_text
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